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Faculty details

Prof.Rahul Bhattacharya

Designation: Assistant Professor

Department: Electronics Engineering

Email: rahul[at]iitism[dot]ac[dot]in

Contact Number:

Office Number: +91-326-223-5129

Personal Page: Click Here

Research Interest: Modelling Of Analog And Mixed-signal Circuits, Fault Modeling And Testing Of VLSI Circuits, FPGA-based Design

Teaching

Theory Courses

Laboratory Courses

UG:

Electronics Engineering,
Basics of Electronics Engineering,
Power Electronics,
Microelectronics and VLSI,
Digital System Design,
Digital System Design using HDL
EDA for VLSI Design

UG:

Electronics Engineering Lab, Power Electronics Lab,
VLSI Design Lab,
Microprocessor & Microcontroller Lab
Electronics Devices and Circuit Lab

PG:

VLSI Circuits Testing,
CAD for VLSI,
Test and Verification of VLSI Circuits,
Digital VLSI Circuits Design

PG:

Microelectronics and VLSI Lab,
Physical Design and EDA Lab
HDL based System Design Lab
VLSI Design and Project Lab

Academics

Position

From June 17, 2013 to till date: Assistant Professor, Department of Electronics Engg., IIT(ISM) Dhanbad.
From March, 2012 to May, 2013: Senior Design Engineer in High Speed Link Validation Group of Wireless Division in ST-Ericsson India Pvt. Ltd, Bangalore, India.
From November, 2010 to March, 2012: Senior Design Engineer in High Speed Link Validation Group of Wireless Division in ST-Ericsson India Pvt. Ltd, Greater Noida, India.
From August, 2006 to October, 2010: Research Consultant in Advanced VLSI Design Laboratory, IIT Kharagpur.
From August, 2005 to August, 2006: Project Engineer in Semiconductor and Consumer Electronics Division in Wipro Technologies, Bangalore.

Awards and Honors

Publications

List Of Research Publications (only in Peer-reviewed Journals)

P. Bhattacharya, R. Bhattacharya, and H. Deka, “MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms”. In: Journal of Electronic Testing: Theory and Applications (Springer Nature), vol. 39, no. 5, 2023, DOI: 10.1007/s10836-023-06088-1.

Rahul Bhattacharya, Subindu Kumar and Santosh Biswas “Fault diagnosis in switched-linear systems by emulation of behavioral models on FPGA: A case study of current-mode buck converter”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Wiley. vol. 31, no. 5, pp. 1-27, 2018.

Rahul Bhattacharya, Subindu Kumar and Santosh Biswas “Resource Optimization for Emulation of Behavioral Models of Mixed Signal Circuits on FPGA: A case study of DC-DC buck converter”, International Journal of Circuit Theory and Applications, Wiley, vol. 45, no. 11, pp. 1701-1741, 2017.

R. Bhattacharya, S. Biswas, S. Mukhopadhyay “FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of Buck converter”, Measurement, Elsevier, vol. 45, issue. 8, pp. 1997-2020, 2012.

Papers in conference abstract volumes / presented

Puja Kumari, Rahul Bhattacharya, “MATLAB-Simulink based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits”, 28^th International Symposium on VLSI Design and Test (VDAT), September 01-03, 2024, Vellore, India. DOI: 10.1109/VDAT63601.2024.10705730

Abuzar Shakeel, Arpita Dey, Rahul Bhattacharya, Roy Vincent, “Emulation of Nonlinear Dynamics of RF Power Amplifier on FPGA”, 9^th IEEE International Conference for Convergence in Technology (I2CT), April 05-07, 2024, Page(s): 01-07

Priyajit Bhattacharya, Abuzar Shakeel, Rahul Bhattacharya, “Fault Emulation in Digital Circuits using FPGA based Software-Hardware Co-Simulation”, 11^th IEEE International Conference on Signal Processing and Integrated Networks (SPIN), March 21-22, 2024, Page(s): 355-360.

Rahul Bhattacharya, S.H.M Ragamai, Subindu Kumar, “SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis”, 21^st International Symposium on VLSI Design and Test (VDAT) 2017, CCIS 711, Springer, pp. 179-190, 2017.

Anjali Rai, Rahul Bhattacharya, “Parametric Fault Detection for Instrumentation Amplifier Circuit”, 2^nd IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur, India.

R. Bhattacharya, S. Kumar, “A New Approach for Modeling Parametric Faults in Linear Analog VLSI Circuits”, 6^th IEEE international conference on Computers and Devices for Communication (CODEC), December 16-18, 2015, DOI: 10.1109/CODEC.2015.7893197

R. Bhattacharya, S. Biswas, S. Mukhopadhyay “FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits”, 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, 2010, Page: 284.

M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay ''A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS'' IEEE Advanced Computing and Communications, 2007. ADCOM 2007, Page(s): 559-566

M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay ''A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS'', IEEE VLSI Design and Test, 2007, Page(s): 196-204.

Projects & Activities

Guidance

Ph.D students registered and ongoing: 01
M.Tech awarded : 19

Sl. No.	Title of M.Tech Thesis	Name of the Student	Year of Completion
1.	Emulation Friendly Modeling of RF Power Amplifier for Pre-Silicon Verification	Abuzar Shakeel	2024
2.	Evolutionary Algorithms for Test Generation of Digital Circuits	Himasree Deka	2024
3.	Emulation of Nonlinearities in RF Power Amplifiers for Pre-Silicon Verification	Arpita Dey	2023
4.	A Framework for Test Generation using Evolutionary Algorithms and FPGA based Fault Emulation in Digital Circuits	Priyajit Bhattacharya	2023
5.	Fault Detection in Analog Circuits using V-transform	Anshul Mahawar	2023
6.	MATLAB-Simulink based Framework for Test Generation of Analog Driven Digital Blocks	Puja Kumari	2022
7.	BIST for DSP CORE in 7-Series FPGA SoC	Shubham Kumar Dokania	2021
8.	V-Transform Coefficient Based Multi-Point Multi-Tone Testing of Analog Circuit	Sourabh Thapar	2021
9.	BIST-based Test for 7-Series FPGA	Ankit Yadav	2020
10.	System Verilog Based Framework for Testing of 7-Series FPGA	Deepshikha	2020
11.	Emulation and Implementation of Switched Capacitor Filters on Field Programmable Gate Array (FPGA)	Rahul Rawat	2020
12.	Emulation and Implementation of Macro-models of Some Analog Circuits on Field Programmable Gate Array (FPGA)	Basant Kumar	2019
13.	FPGA based BIST for Digital Circuits	Abhishek Raj	2018
14.	Digital Circuit Design and Implementation using FPGA	Amit Choudhary	2017
15.	Parametric Fault Detection in Linear Analog Circuits	Anjali Rai	2017
16.	Fault Simulation and Fault Diagnosis in Linear and Switched Linear Circuits	S.H.M Ragamai	2017
17.	Fault Modeling of Linear and Non-linear Analog Circuits	Lokesh Gupta	2016
18.	Fault Modeling of Analog VLSI Circuits in a Digital Platform	Nilam Hansda	2016
19.	Fault Modeling and Test Generation of Analog VLSI Circuits	Sandeep Thakur	2015

Title of the Project	Sponsoring Agency	Duration	Amount (in Lakhs)	Role
Bandwidth Adaptive RF Power Amplifier Modeling for Cross Bandwidth Testing (Under ADI Innovation Fellowship Grant)	Analog Devices India Pvt. Ltd. Bangalore	1 year (from July 2024 to June 2025)	4.047	PI
Emulation Friendly Modeling of RF Power Amplifier for Pre-Silicon Verification *(Under ADI Innovation Fellowship Grant)*	Analog Devices India Pvt. Ltd. Bangalore	1 year (from July 2023 to June 2024)	4.72	PI
Ultra-Low Power Neuromorphic Spiking Architecture for Assistive Smart Glasses	MEITY, Govt. of India	5 years (from 2022 to 2027)	86	Co-PI
Test development of analog and mixed signal circuits by emulation and implementation of their behavioral models on FPGA	*IIT (ISM) Dhanbad (under Faculty Research Scheme)*	3 years (from Feb,2015)	7.91	PI
Feasibility study on fault emulation of linear analog circuits on a programmable hardware	IIT (ISM) Dhanbad (under the aegis of TEQIP-II)	6 months (from Nov, 2016)	2.00	PI

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